View ADP3414JRZ_2098730.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adp3414 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual bootstrapped mosfet driver functional block diagram in vcc overlap protection circuit bst drvh sw drvl pgnd adp3414 features all-in-one synchronous buck driver bootstrapped high side drive one pwm signal generates both drives anticross-conduction protection circuitry pulse-by-pulse disable control applications mobile computing cpu core power converters multiphase desktop cpu supplies single-supply synchronous buck converters standard-to-synchronous converter adaptations general description the adp3414 is a dual mosfet driver optimized for driving two n-channel mosfets which are the two switches in a nonisolated synchronous buck power converter. each of the drivers is capable of driving a 3000 pf load with a 20 ns propa- gation delay and a 30 ns transition time. one of the drivers can be bootstrapped and is designed to handle the high voltage sle w rate associated with floating high side gate drivers. the adp3414 includes overlapping drive protection (odp) to prevent shoot-through current in the external mosfets. the adp3414 is specified over the commercial temperature r ange of 0 c to 70 c and is available in an 8-lead soic package. in vcc adp3414 bst drvh sw drvl pgnd delay 1v +1v 12v c bst 7v q1 q2 d1 figure 1. general application circuit
rev. a e2e adp3414especifications 1 parameter symbol conditions min typ max unit supply supply voltage range vcc 4.15 7.5 v quiescent current icc q 12 ma pwm input input voltage high 2 2.3 v input voltage low 2 0.8 v high side driver output resistance, sourcing current v bst ? v sw = 5 v 3.0 5.0 v bst ? v sw = 7 v 2.0 3.5 output resistance, sinking current v bst ? v sw = 5 v 1.25 2.5 v bst ? v sw = 7 v 1.0 2.5 transition times 3 (see figure 2) tr drvh v bst ? v sw = 7 v, c load = 3 nf 36 47 ns tf drvh v bst ? v sw = 7 v, c load = 3 nf 20 30 ns propagation delay 3, 4 (see figure 2) tpdh drvh v bst ? v sw = 7 v 65 86 ns tpdl drvh v bst ? v sw = 7 v 21 32 ns low side driver output resistance, sourcing current vcc = 5 v 3.0 5.0 vcc = 7 v 2.0 3.5 output resistance, sinking current vcc = 5 v 1.5 3.0 vcc = 7 v 1.0 2.5 transition times 3 (see figure 2) tr drvl vcc = 7 v, c load = 3 nf 27 35 ns tf drvl vcc = 7 v, c load = 3 nf 19 26 ns propagation delay 3, 4 (see figure 2) tpdh drvl vcc = 7 v 30 35 ns tpdl drvl vcc = 7 v 15 25 ns notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 logic inputs meet typical cmos i/o conditions for source/sink current (~1 a). 3 ac specifications are guaranteed by characterization but not production tested. 4 for propagation delays, ? tpdh ? refers to the specified signal going high; ? tpdl ? refers to it going low. specifications subject to change without notice. (t a = 0 c to 70 c, vcc = 7 v, bst = 4 v to 26 v, unless otherwise noted.)
rev. a adp3414 ? absolute maximum ratings * vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +8 v bst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +30 v bst to sw . . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +8 v sw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 5.0 v to +25 v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to vcc + 0.3 v operating ambient temperature range . . . . . . . 0 c to 70 c operating junction temperature range . . . . . . 0 c to 125 c ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 c/w jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c/w storage temperature range . . . . . . . . . . . . C 65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c * this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. unless otherwise specified, all voltages are referenced to pgnd. pin configuration in vcc bst nc drvh sw drvl pgnd 8 7 6 5 nc = no connect adp3414 top view (not to scale) 1 2 3 4 pin function descriptions pin mnemonic function 1 bst floating bootstrap supply for the upper mosfet. a capacitor connected between bst and sw pins holds this bootstrapped voltage for the high side mosfet as it is switched. the capacitor should be chosen between 100 nf and 1 f. 2i n ttl-level input signal that has primary control of the drive outputs. 3n c no connection 4 vcc input supply. this pin should be bypassed to pgnd with ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output drive for the lower (synchronous rectifier) mosfet. 6 pgnd power ground. should be closely connected to the source of the lower mosfet. 7s w this pin is connected to the buck-switching node, close to the upper mosfet s source. it is the floating return for the upper mosfet drive signal. it is also used to monitor the switched voltage to prevent turn- on of the lower mosfet until the voltage is below ~1 v. thus, according to operating conditions, the high low transition delay is determined at this pin. 8 drvh buck drive. output drive for the upper (buck) mosfet. ordering guide temperature package package model range description option adp3414jr 0 c to 70 c8 -lead standard soic-8 small outline (soic) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3414 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a adp3414 e4e in drvh-sw drvl sw tpdl drvl tf drvl tr drvl tpdl drvh tf drvh tpdh drvh tr drvh v th v th 1v tpdh drvl figure 2. nonoverlap timing diagram (timing is referenced to the 90% and 10% points unless otherwise noted)
rev. a adp3414 e5e t ypical performance characteristicse r1 r2 r3 t in drvh 5v/div 2v/div drvl 5v/div 40ns/div t a = 25 c vcc = 5v tpc 1. drvh fall and drvl rise times junction temperature e c time e ns 0 0 25 125 50 75 100 5 10 15 20 25 30 35 drvh @ vcc = 7v drvl @ vcc = 7v drvh @ vcc = 5v drvl @ vcc = 5v tpc 4. drvh and drvl fall times vs. temperature in frequency e khz supply current e ma 0 0 200 400 600 800 5 10 15 20 25 30 35 1000 1200 1400 t a = 25 c c load = 3nf vcc = 5v vcc = 7v tpc 7. supply current vs. frequency r1 r2 r3 t drvh 5v/div in 2v/div drvl 2v/div 40ns/div t a = 25 c vcc = 5v tpc 2. drvl fall and drvh rise times load capacitance e nf time e ns 10 1.0 15 25 35 45 55 2.0 3.0 4.0 5.0 drvh @ vcc = 7v drvl @ vcc = 7v drvh @ vcc = 5v drvl @ vcc = 5v 50 40 30 20 tpc 5. drvh and drvl rise times vs. load capacitance supply current e ma junction temperature e c 5.0 0 25 50 75 100 5.5 6.0 6.5 7.0 7.5 8.0 8.5 125 c load = 3nf f in = 250khz vcc = 7v vcc = 5v tpc 8. supply current vs. temperature junction temperature e c time e ns 025 125 50 75 100 20 25 30 35 40 45 50 drvh @ vcc = 7v drvh @ vcc = 5v drvl @ vcc = 5v drvl @ vcc = 7v c load = 3nf tpc 3. drvh and drvl rise times vs. temperature load capacitance e nf time e ns 7 1.0 2.0 3.0 4.0 5.0 12 17 22 27 32 37 drvh @ vcc = 7v drvl @ vcc = 7v drvh @ vcc = 5v drvl @ vcc = 5v 1.5 2.5 3.5 4.5 tpc 6. drvh and drvl fall times vs. load capacitance
rev. a adp3414 e6e theory of operation the adp3414 is a dual mosfet driver optimized for driving tw o n-channel mosfets in a synchronous buck converter topol ogy. a single pwm input signal is all that is required to properly drive the high side and the low side fets. each driver is capable of dr iving a 3 nf load. a more detailed description of the adp3414 and its features follows. refer to the functional block diagram. low side driver th e low side driver is designed to drive low r ds(on) n- channel m osfets. the maximum output resistance for the driver is 3.5 for sourcing and 2.5 for sinking gate current. the low output resistance allows the driver to have 20 ns rise and fall times into a 3 nf load. the bias to the low side driver is inter- nally connected to the vcc supply and pgnd. when the driver is enabled, the driver ? s output is 180 degrees out of phase with the pwm input. when the adp3414 is dis- abled, the low side gate is held low. high-side driver the high side driver is designed to drive a floating low r ds(on) n-channel mosfet. the maximum output resistance for the d river is 3.5 for sourcing and 2.5 for sinking gate cur- rent. the low output resistance allows the driver to have 30 ns rise and fall times into a 3 nf load. the bias voltage for the high side driver is developed by an external bootstrap supply circuit, which is connected between the bst and sw pins. th e bootstrap circuit comprises a diode, d1, and bootstrap capacitor, c bst . when the adp3414 is starting up, the sw pin is at ground, so the bootstrap capacitor w ill charge up to vcc th rough d1. when the pwm input goes high, the high side driver will begin to turn the high side mosfet, q1, on by pulling charge out of c bst . as q1 turns on, the sw pin will rise up to v in , forcing the bst pin to v in + v c(bst) , which is enough gate to source voltage to hold q1 on. to complete the cycle, q1 is switched off by pulling the gate down to the volt- age at the sw pin. when the low side mosfet, q2, turns on, the sw pin is pulled to ground. this allows the bootstrap capacitor to charge up to vcc again. the high-side driver ? s output is in phase with the pwm input. when the driver is disabled, the high side gate is held low. overlap protection circuit the overlap protection circuit (opc) prevents both of the main power switches, q1 and q2, from being on at the same time. t his is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on-off transitions. the overlap protection c ircuit accomplishes this by adaptively controlling the delay from q1 ? s turn off to q2 ? s turn on and by internally setting the delay from q2 ? s turn off to q1 ? s turn on. to prevent the overlap of the gate drives during q1 ? s turn off a nd q2 ? s turn on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, q1 will begin to turn off (after a propagation delay), but before q2 can turn on, the overlap protection circuit waits for the voltage at the sw pin to fall from v in to 1 v. once the voltage on the sw pin has fallen to 1 v, q2 will begin turn on. by waiting for the voltage on the sw pin to reach 1 v, the overlap protection circuit ensures that q1 is off before q2 turns on, regardless of variations in tem- perature, supply voltage, gate charge, and drive current. to prevent the overlap of the gate drives during q2 ? s turn off and q1 ? s turn on, the overlap circuit provides a internal delay that is set to 50 ns. when the pwm input signal goes high, q2 will begin to turn off (after a propagation delay), but before q1 can turn on, the overlap protection circuit waits for the voltage at drvl to drop to around 10% of vcc. once the voltage at drvl has reached the 10% point, the overlap protec- tion circuit will wait for a 20 ns typical propagation delay. once the delay period has expired, q1 will begin turn on. application information supply capacitor selection for the supply input (vcc) of the adp3414, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. use a 1 f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size and can be obtained from the following vendors: murata grm235y5v106z16 www.murata.com taiyo- yuden emk325f106zf www.t-yuden.com tokin c23y5v1c106zp www.tokin.com keep the ceramic capacitor as close as possible to the adp3414. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and a schottky diode, as shown in figure 1. selection of these compo- nents can be done after the high side mosfet has been chosen. the bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 v. a minimum 50 v rating is recommended. the capacitance is determined us ing the following equation: c q v bst gate bst = where, q gate is the total gate charge of the high side mosfet, and v bst is the voltage droop allowed on the high side mosfet drive. for example, the irf7811 has a total gate charge of about 20 nc. for an allowed droop of 200 mv, the required boot- strap capacitance is 100 nf. a good quality ceramic capacitor should be used. a schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high side mosfet. the bootstrap diode must have a mini- mum 40 v rating to withstand the maximum battery voltage plus 5 v. the average forward current can be estimated by: iqf f(avg) gate max where f max is the maximum switching frequency of the control- ler. the peak surge current rating should be checked in-circuit, since this is dependent on the source impedance of the 5 v supply and the esr of c bst .
rev. a adp3414 e7e printed circuit board layout considerations use the follo wing general guidelines when designing pr inted circuit boards: 1. trace out the high current paths and use short, wide traces to make these connections. 2. connect the pgnd pin of the adp3414 as close as possible to the source of the lower mosfet. 3. the vcc bypass capacitor should be located as close as possible to vcc and pgnd pins. in vcc bst drvh sw drvl pgnd 8 7 6 5 1 2 3 4 u2 adp3414 nc + + + + + + vid4 vcc u1 adp3160 vid3 vid2 vid1 vid0 comp fb ct ref cse pwm1 pwm2 cs+ pwrgnd gnd in vcc bst drvh sw drvl pgnd 8 7 6 5 1 2 3 4 u3 adp3414 nc q1 fdb7030l q3 fdb7030l q2 fdb8030l l2 600nh c11 c16 c17 c18 c19 c20 c27 c28 + + v cc (core) 1.1v e 1.85v 53.4a v cc (core) rtn 1200 f 8 osecon 2.5v 11m esr (each) l1 600nh q4 fdb8030l c5 1 f c9 1 f d1 mbr052lti r4 4m r7 20 r5 2.4k c26 4.7 f z1 zmm5236bct q5 2n3904 c22 1nf c4 4.7 f r6 10 c21 15nf c6 1 f c10 1 f d2 mbr052lti from cpu r z 1.1k c1 150pf c oc 1.4nf r b 11.5k r1 1k c2 100pf r a 34.0k c15 c14 c13 c12 v in 12v v in rtn 270 f 4 osecon 16v nc = no connect c23 10 f c24 10 f 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 figure 3. 53.4 a intel cpu supply circuit typical application circuits the circuit in figure 3 shows how two drivers can be com- bined with the adp3160 to form a total power conversion solution for v cc(core) generation in a high current intel cpu com puter. figure 4 gives a similar application circuit for a 45 a amd processor.
rev. a adp3414 e8e in vcc bst drvh sw drvl pgnd 8 7 6 5 1 2 3 4 u2 adp3414 nc + + + + + + 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vid4 vcc u1 adp3160 vid3 vid2 vid1 vid0 comp fb ct ref cse pwm1 pwm2 cs+ pwrgd gnd in vcc bst drvh sw drvl pgnd 8 7 6 5 1 2 3 4 u3 adp3414 nc q1 fdb7030l q3 fdb7030l q2 fdb7045l l2 600nh c11 c16 c17 c18 c19 c20 c27 c28 + + v cc (core) 1.1v e 1.85v 45a v cc (core) rtn 1000 f 8 rubycon za series 24m esr (each) l1 600nh q4 fdb7045l c5 1 f c9 1 f d1 mbr052lti r4 5m r7 20 r5 2.4k c26 4.7 f z1 zmm5236bct q5 2n3904 c22 1nf c4 4.7 f r6 10 c21 15nf c6 1 f c10 1 f d2 mbr052lti from cpu r z 750 c1 150pf c oc 4.7nf r b 14.0k r1 1k c2 100pf r a 6.98k c15 c14 c13 c12 v in 5v v in rtn 1000 f 6 rubycon za series 12v v cc 12v v cc rtn c24 c25 nc = no connect c29 10 f c30 10 f figure 4. 45 a athlon duron cpu supply circuit
rev. a adp3414 e9e 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) pin 1 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa outline dimensions
rev. a adp3414 e10e revision history location page 08/02?data sheet changed from rev. 0 to rev. a. updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
e11e
?2 c02400??/02(a) printed in u.s.a.

▲Up To Search▲

Price & Availability of ADP3414JRZ

	To Download ADP3414JRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .